• Ooi Chek Yee Faculty of Information and Communication Technology, Universiti Tunku Abdul Rahman, Malaysia
  • Mok Kai Ming Faculty of Information and Communication Technology, Universiti Tunku Abdul Rahman, Malaysia
  • Wong Pei Voon Faculty of Information and Communication Technology, Universiti Tunku Abdul Rahman, Malaysia


The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit.

Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed


[1] Reza Hosseini and Neda Teimuorzadeh, “Simulation Study of Circuit Performance of GAA Silicon Nanowire Transistor and DG MOSFET”, Physical Review & Research International, 3(4): 568-576, 2013.

[2] P. A. Gowri Sankar and K. Udhayakumar, “MOSFET-like CNFET Based Logic Gate Library for Low-power Application: A Comparative Study”, Journal of Semiconductors, Vol. 35, No. 7, 2014.

[3] Ulrich Wulf, Marcus Krahlisch and Hans Richter, “Scaling Properties of Ballistic Nano-transistors”, Nanoscale Research Letters, 6:365, 2011.

[4] Manorama, Pavan Shrivastava and Shyam Akashe, “Design and Analysis of Leakage Current and Delay for Double-Gate MOSFET at 45nm in CMOS Technology”, IEEE, 978-1-4673-4603-0, 2012.

[5] A. Abdolahzadeh Ziabari, M. Charmi and H. R. Mashayekhi, “The Impact of Body Doping Concentration on the Performance of Nano DG-MOSFETs: A Quantum Simulation”, Chinese Journal of Physics, Vol. 51, No. 4: 844-853, 2013.

[6] Changwook Jeong, Dimitri Antoniadis and Mark S. Lundstrom, “On Backscattering and Mobility in Nanoscale Silicon MOSFETs”, IEEE Transactions on Electron Devices, Vol. 56, No. 11: 2762-2769, 2009.

[7] Marc Baldo, “Introduction to Nanoelectronics”, MIT Open Course Ware Publication, 2011.

[8] George W. Hanson, “Fundamentals of nanoelectronics”, Pearson International Edition, 2008.

[9] Microsystem Technologies, “Design of 4 nm MOSFET and Its Applications”, Springer Technical Paper, 25 July 2018.

[10] K. Navi, M. Rashtian, A. Khatir, P. Keshavarzian and O. Hashemipour, “High Speed Capacitor-inverter Based Carbon Nanotube Full Adder”, Nanoscale Research Letters, 5:859-86, 2010.

[11] Michael Loong Peng Tan, Georgios Lentaris and Gehan AJ Amaratunga, “Device and Circuit-level Performance of Carbon Nanotube Field-Effect Transistor with Benchmarking against A Nano-MOSFET”, Nanoscale Research Letters, 7:467, 2012.

[12] Huei Chaeng Chin, Cheng Siong Lim, Weng Soon Wong and Michael Loong Peng Tan, “Enhanced Device and Circuit-level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against A Nano-MOSFET with Interconnects”, Journal of Nanomaterials, Vol. 2014, Article ID 879813, 2014.

[13] Abhishek Verma, Anup Mishra and Padmadhar Mishra, “Scaling of Dimensions & Gate Capacitances of MOSFET”, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), Volume 1, Issue 9, November 2012.

[14] Rohini Gupta, Bogdan Tutuianu and Lawrence T. Pileggi, “The Elmore Delay as A Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 1, 95-104, 1997.

[15] Yiming Li and Chih-Hong Hwang, “High-frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants”, IEEE Transactions on Microwave Theory and Techniques, Vol. 56, No. 12, 2726-2733, 2008.

[16] Ming-Hung Han, Yiming Li and Chih-Hong Hwang, “The Impact of High-frequency Characteristics Induced by Intrinsic Parameter Fluctuations in Nano-MOSFET Device and Circuit”, Microelectronics Reliability, 50, 657-661, 2010.

[17] A. A. A. Nasser, Moustafa H. Aly, Roshdy A. Abdel Rassoul, Ahmed Khourshed, “Performance of Near-ballistic Limit Carbon Nano-Transistor (CNT) Circuits”, ICCTA, 175-182, 2011.

[18] Hesham F. A. Hamed, Savas Kaya and Janusz A. Starzyk, “Use of Nano-scale Double-Gate MOSFETs in Low-power Tunable Current Mode Analog Circuits”, Analog Integr Circ Sig Process, doi 10.1007/s10470-008-9134-4, 2008.

[19] Kousik Naskar, C. J. Clement Singh and Subir Kumar Sarkar, “Analytical Modeling of SON MOSFET and Realization Inverter Circuit for High Speed and Ultra Dense Low Power Circuits”, Journal of Nano- and Electronic Physics, Vol. 4, No. 2, 02023(5pp), 2012.

[20] Rakesh Prasher, Devi Dass and Rakesh Vaid, “Performance of a Double Gate Nanoscale MOSFET (DG-MOSFET) Based on Novel Channel Materials”, Journal of Nano- and Electronic Physics, Vol. 5, No. 1, 01017(5pp), 2013.

[21] Zhibin Ren, “Nanoscale MOSFETs: Physics, Simulation and Design”, Ph.D. Dissertation, Purdue University, 2001.

[22] Mark Lundstrom, “Notes on the Ballistic MOSFET”, Network for Computational Nanotechnology, Purdue University, 2005.

[23] Raseong Kim and Mark Lundstrom, “Notes on Fermi-Dirac Integrals”, Network for Computational Nanotechnology, Purdue University, 2011.

[24] Ooi Chek Yee and Lim Soo King, “Simulation Study on the Electrical Performance of Equilibrium Thin-body Double-Gate Nano-MOSFET”, Jurnal Teknologi, Vol. 76, 87-95, 2015.

[25] Ooi Chek Yee and Lim Soo King, “Simulation Study of 2D Electron Density in Primed and Unprimed Subband Thin-body Double-Gate Nano-MOSFET of Three Different Thicknesses and Two Temperature States”, International Journal of Nanoelectronics and Materials, Vol. 9, 67-84, 2016.

[26] Sanjeet Kumar Sinha and Saurabh Chaudhury, “Simulation and Analysis of Quantum Capacitance in Single-Gate MOSFET, Double-Gate MOSFET and CNTFET Devices for Nanometer Regime”, IEEE 978-1-4673-4700-6, 2012.
How to Cite
CHEK YEE, Ooi; KAI MING, Mok; PEI VOON, Wong. DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs. Platform : A Journal of Science and Technology, [S.l.], v. 4, n. 1, p. 73-84, may 2021. ISSN 2637-0530. Available at: <>. Date accessed: 24 june 2024. doi: