Yield Improvement of Wafer Edge Die Defocus at Lithography Process for 0.16µm CMOS Technology
The lithography process is the heart of the semiconductor process. The process is to transfer the circuit design on the wafer substrate via reticle at the expansive lithography equipment. It’s a critical process, where any defects if not detected caused scrap to wafers of deformity found in the pattern a possible rework with series of etching and cleaning equipment needed that easily took a day loss of cycle time in the hectic high utilization manufacturing facility. The research focuses on the new technology of 0.16µm that facing an issue of poor pattern formation at the edge of the wafer and its damage area will be the show stopper to introduce for high volume manufacturing. This research is focus to minimize the defects by optimizing the process recipe Improve Inner & Edge Die Bias (IIEDB) being explored at the Deep Ultra Violet (DUV) 193nm wavelength equipment. The recipes that combine the temperature of baking and radial exposure parameters help significantly to reduce the defect. Measurement of good die versus bad die of a wafer unit in percentage being used for an electrical and functional test that also known as sort yield is used in the paper. The new finding has shown significant results to reduce yield loss issues at the edge region and able to improve the edge die sort yield from 50% to 85% and the electrical yield from 81% to 94%. This paper will discuss the journey for edge die defocus improvement.
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